1. Field of the Invention
The present invention relates to a method of forming a semiconductor device and, more particularly, to a method of forming an inductor.
2. Description of Related Art
An inductor is used to apply a complementary metal oxide semiconductor (CMOS) technology to radio-frequency integrated circuits. An inductor is a passive device that is necessary for impedance matching in a high-frequency integrated circuit. Particularly, an inductor used in a high-frequency integrated circuit is required for a high quality factor to reduce phase noise.
FIG. 1 illustrates a cubic structure of a conventional inductor used in a high-frequency integrated circuit and an equivalent circuit diagram thereof. In FIG. 1, Ls denotes a total inductance of a self inductance of a spiral inductor and a mutual inductance between metal lines constituting the inductor; Rs denotes a sum of a DC resistance of the inductor and an AC resistance considering skin effect occurring at a high frequency; Cs denotes a capacitance of a parasitic capacitor formed between metal lines; Cp denotes a capacitance of a parasitic capacitor formed between an inductor and a substrate, the Cp being calculated from a thickness of an insulation layer formed between the substrate and the inductor; and Rp denotes a superhigh frequency leakage effect of a silicon substrate, the superhigh frequency leakage effect being modeled with resistors.
An entire quality factor (Q) of the equivalent circuit shown in FIG. 1 is expressed by the following equation [Equation 1].
                    Q        =                                            Magnetic              ⁢                                                          ⁢              Energy              ⁢                                                          ⁢                              (                Em                )                                      -                          Electric              ⁢                                                          ⁢              Energy              ⁢                                                          ⁢                              (                Ee                )                                                          Energy            ⁢                                                  ⁢            Loss            ⁢                                                  ⁢                          (              Eloss              )                                                          [                  Equation          ⁢                                          ⁢          1                ]            
The magnetic energy (Em), electric energy (Ee), and energy loss (Eloss) of Equation 1 are obtained by the following equations [Equation 2] through [Equation 4], respectively.
                    Em        =                                            V              2                        ⁢            wLs                                2            ⁡                          [                                                                    (                    wLs                    )                                    2                                +                                  Rs                  2                                            ]                                                          [                  Equation          ⁢                                          ⁢          2                ]                                Ee        =                                            V              2                        ⁢                          w              ⁡                              (                                  Cs                  +                  Cp                                )                                              2                                    [                  Equation          ⁢                                          ⁢          3                ]                                Eloss        =                                            V              2                        2                    ⁡                      [                                          1                Rp                            +                              Rs                                                                            (                      wLs                      )                                        2                                    +                                      Rs                    2                                                                        ]                                              [                  Equation          ⁢                                          ⁢          4                ]            
Referring to Equation 2 through Equation 4, V denotes voltage and w denotes frequency. With the rise of capacitances Cs and Cp of a parasitic capacitor formed by coupling with Rs, the magnetic energy Em becomes greater while electrical energy Ee and energy loss Eloss become smaller. Further, the rise of the capacitance Cs and Cp may result in a higher quality factor which may be obtained by Equation 1. Accordingly, there is a need to reduce a resistance of a conductive layer and a capacitance of a sacrificial capacitor in order to obtain a higher quality factor.
Conventionally, several approaches have been suggested to reduce a capacitance of a parasitic capacitor. One of the approaches is that a grounding metal layer is formed on a substrate to perform shielding, and another is that an inductor is formed and a substrate below the inductor is etched. Unfortunately, these conventional approaches need an extra CMOS process, which increases process cost.
FIG. 2 is a cross-sectional view of a conventional inductor. In the inductor illustrated in FIG. 2 is that metal layers increase in number while reducing a resistance Rs of a conductive layer in order to obtain a high quality factor taking into consideration the above issues, which is disclosed in U.S. Pat. No. 6,062,161.
Referring to FIG. 2, a first insulation layer 5 is formed on a substrate 1. A first conductive pattern 20 is formed on the first insulation layer 5. A second insulation layer 7 is stacked and a second conducive pattern 10 is formed on the first conductive pattern 20. The first and second conductive patterns 20 and 10 are interconnected by a contact hole 30 to constitute an inductor, which result in the effect that a thickness of a conductive layer increases. Thus, a resistance of the conductive layer decreases. A lead wiring 20A connected through a contact hole is formed to results in decreasing the number of entire metal layers. A reference number 10A denotes a lead wiring connected to the second conductive pattern 10, as illustrated in FIG. 1.
As previously stated, a resistance of a conductive layer is equal to sum of DC resistance and an AC resistance reflecting the skin effect arising at a superhigh frequency, of an inductor. An inductor illustrated in FIG. 2 may have an effect to reduce a DC resistance by increasing thickness of a metal layer but may not have an effect to enhance the skin effect arising at a superhigh frequency.
In view of the foregoing, there is a need for a method for forming a an inductor of high-quality factor where a thickness of metal used in the inductor increases to reduce a resistance thereof while reducing the skin effect arising at a superhigh frequency.